FPGA实现
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/08/19 19:42:08
// Design Name:
// Module Name: img_horizion_flip
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module img_horizion_flip(input clk ,input rst ,input [ 10: 0] img_width ,input [ 23: 0] img_data_i ,input valid_i ,output reg [ 23: 0] img_data_o ,output reg valid_o
);reg wr_flag ;reg [ 10: 0] addr
