FPGA实现
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/08/25 12:56:19
// Design Name:
// Module Name: img_rotate
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module img_rotate#(parameter angle = 90 //旋转角度
)(input clk ,input rst ,input [ 11: 0] img_new_width ,input [ 11: 0] img_new_height ,input wire [ 11: 0] img_width ,input wire [ 10: 0] img_height ,input valid_i ,input [ 23: 0] img
